1. Field of the Invention
The present invention relates to a device and method for managing wait cycles while reading a nonvolatile memory, in particular a flash memory integrated with a low pin count (LPC) interface for PCBios applications and using one of the serial communication protocols forming part of the family protocols of the LPC type.
2. Description of the Related Art
As is known, when reading or writing is to be performed in a memory that uses a communication protocol, an external device or “host,” sends, on the system bus connecting the memory itself to the host device, in a timely sequential way and according to a pre-determined sequence of cycles, codes and information forming, as a whole, the communication protocol itself. The codes, regarding commands to be executed, and the information, regarding the addresses, are decoded in one clock cycle.
The pattern of the cycles provided in a generic communication protocol of the LPC type may be divided into two fundamental parts: one first step when the external host controls the bus, and a second step when the bus control is handed over to the memory.
During the first step, the host supplies the codes for a read/write operation in a memory array, as well as the addresses of the byte to be read/written.
Next, two turn-around (TAR) cycles, TAR_1 and TAR_2, are provided, the second of which corresponds to a high-impedance condition.
In particular, by way of example, FIG. 1 shows the set of the clock cycles with the corresponding codes, for the I/O Cycles communication protocol.
The protocol of FIG. 1 (starting from instant t0) comprises a START cycle, which enables all the rest of the protocol, a CYCT+DIR cycle, during which it is specified whether a memory-array reading or writing operation is to be performed, eight address cycles (ADDR) and the two TAR cycles (TAR_1 and TAR_2). During the latter two cycles, the host hands over control of the bus system to the memory.
Subsequently, during the second step, it is the memory itself that controls the bus system and generates a series of SYNC or wait cycles, the last of which, designated as SYNC_E, is a ready signal and has a value different from the previous ones, to signal when the data are ready to be supplied outside; then the memory sends out the data read, divided between the first four bits (DL cycle) and the second four bits (DH cycle), thus terminating the protocol.
The SYNC cycles (including the last one, SYNC_E) define wait states during which the memory must perform all the operations necessary for reading the word addressed and set the requesting host device in a listening state until the results arrive. Normal SYNC cycles (except for the last one, SYNC_E) generally have two different values according to whether a long wait or a short wait is envisaged. According to the type of serial communication protocol used, the number of short wait cycles (SYNC) can have a maximum admissible value, which cannot be exceeded.
With the protocol described, the total maximum number of short wait cycles (including the last one, SYNC_E) is eight; if the memory outputs a number of short cycles exceeding eight, the host device aborts the reading cycle.
At present, the overall number of wait cycles SYNC is fixed beforehand (i.e., via hardware), taking into account the size of the memory used (currently, from 2 to 32 Mb), the supply voltage (currently, 1.8 V, 3.3 V or 5 V, which determines different access times), the reading type (for example, in burst mode the time taken by the memory for performing the first reading and the time taken to perform the subsequent readings are very different, resulting in different wait times in the two cases), the technology of memory (which determines performance thereof), and the speed of the clock (currently 33 or 66 MHz).
For example, with a memory core having an access time of less than 90 ns and a 33-MHz clock, three wait cycles are generally sufficient to synchronize internal reading with the step of supplying the data read outwards.
This is disadvantageous, in so far as it requires an evaluation, often also on silicon, of the response times of the memory, as well as modification, via hardware, of the communication protocol, to adapt it to the existing conditions.